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general description the max5732?ax5735 are 32-channel, 16-bit, voltage- output, digital-to-analog converters (dacs). all devices accept a 3v external reference input. the devices include an internal offset dac that allows all the outputs to be offset and a ground-sensing function, allowing out- put voltages to be referenced to a remote ground. a 33mhz spi-/qspi-/microwire- and digital signal processor (dsp)-compatible serial interface con- trols the max5732?ax5735. each dac has a double- buffered input structure that helps minimize the digital noise feedthrough from the digital inputs to the outputs, and allows for synchronous or asynchronous updating of the outputs. the max5732?ax5735 also provide a dout that allows for read-back or daisy chaining multi- ple devices. the devices provide separate power inputs for the analog and digital sections and provide separate power inputs for the output buffer amplifiers. the max5732?ax5735 include proprietary deglitch circuits to prevent output glitches at power-up and eliminate the need for power sequencing. the devices provide a software-shutdown mode to allow efficient power management. the max5732?ax5735 con- sume 50? of supply current in shutdown. the max5732?ax5735 provide buffered outputs that can drive 10k ? in parallel with 100pf. the max5732 has a 0 to +5v output range; the MAX5733 has a 0 to +10v range; the max5734 has a -2.5v to +7.5v range; the max5735 has a -5v to +5v range. the max5732 max5735 are available in a 56-pin, 8mm x 8mm, thin qfn package in both the commercial (0? to +70?) and extended (-40? to +85?) temperature ranges. applications automatic test systems optical router controls industrial process controls arbitrary function generators avionics equipment digital offset/gain adjustment features ? guaranteed monotonic to 16 bits ? 32 individual dacs in an 8mm x 8mm, 56-pin, thin qfn package ? four output voltage ranges 0 to +5v 0 to +10v -2.5v to +7.5v -5v to +5v ? buffered voltage outputs capable of driving 10k ? || 100pf ? glitch-free power-up ? spi-/qspi-/microwire-/dsp-compatible 33mhz serial interface max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface ________________________________________________________________ maxim integrated products 1 ordering information 19-3148; rev 4; 12/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max5732 actn* 0? to +70? 56 thin qfn-ep** max5732bctn 0? to +70? 56 thin qfn-ep** max5732cctn 0? to +70? 56 thin qfn-ep** max5732aetn* -40? to +85? 56 thin qfn-ep** max5732betn -40? to +85? 56 thin qfn-ep** max5732cetn -40? to +85? 56 thin qfn-ep** MAX5733 actn* 0? to +70? 56 thin qfn-ep** MAX5733bctn 0? to +70? 56 thin qfn-ep** MAX5733cctn 0? to +70? 56 thin qfn-ep** MAX5733aetn* -40? to +85? 56 thin qfn-ep** MAX5733betn -40? to +85? 56 thin qfn-ep** MAX5733cetn -40? to +85? 56 thin qfn-ep** max5734 actn* 0? to +70? 56 thin qfn-ep** max5734bctn 0? to +70? 56 thin qfn-ep** max5734cctn 0? to +70? 56 thin qfn-ep** max5734aetn* -40? to +85? 56 thin qfn-ep** max5734betn -40? to +85? 56 thin qfn-ep** max5734cetn -40? to +85? 56 thin qfn-ep** max5735 actn* 0? to +70? 56 thin qfn-ep** max5735bctn 0? to +70? 56 thin qfn-ep** max5735cctn 0? to +70? 56 thin qfn-ep** max5735aetn* -40? to +85? 56 thin qfn-ep** max5735betn -40? to +85? 56 thin qfn-ep** max5735cetn -40? to +85? 56 thin qfn-ep** spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. pin configuration and selector guide appear at end of data sheet. * future product?ontact factory for availability. specifications are preliminary. ** ep = exposed paddle (internally connected to v ss ).
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics?ax5732 (0 to +5v output voltage range) (av cc = +5.25v to +5.5v (note 1), av dd = +5v ?%, dv dd = +2.7v to av dd , v ss = agnd = dgnd = refgnd = gs = 0, v ref = +3.0v, r l = , c l = 50pf referenced to ground, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av cc to v ss , agnd, dgnd, refgnd ..................-0.3v to +12v v ss to agnd, dgnd................................................-6v to +0.3v av dd , dv dd to agnd, dgnd, refgnd.................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v ref to agnd, d gnd, refgnd...............-0.3v to the lower of (av dd + 0.3v) and +6v refgnd to agnd.................................................-0.3v to +0.3v digital inputs to agnd, dgnd, refgnd..............-0.3v to the lower of (dv dd + 0.3v) and +6v dout to dgnd.......-0.3v to the l ower of (dv dd + 0.3v) and +6v out_ to v ss .........-0.3v to the lower of (av cc + 0.3v) and +12v gs to agnd ................................................................-1v to +1v maximum current into ref...............................................?0ma maximum current into any pin .........................................?0ma continuous power dissipation (t a = +70?) thin qfn (derate 31.3mw/? above +70?)...................2.5w operating temperature ranges max573__ctn....................................................0? to +70? max573__etn .................................................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc characteristics resolution n 16 bits max5732b ? ?6 integral nonlinearity (note 2) inl max5732c ?2 ?4 lsb differential nonlinearity dnl guaranteed monotonic (note 3) ? lsb zero-scale error v os v ss = -0.5v, av cc = +5.25v (note 4) ? ?0 mv full-scale error (note 4) ? ?0 mv gain error ?.1 ?.5 %fsr gain temperature coefficient 20 40 ppm fsr/? dc crosstalk v ss = -0.5v, av cc = +5v (note 5) 50 250 ? dynamic characteristics output-voltage settling time full-scale change to ?.5 lsb 20 ? voltage-output slew rate 1 v/? digital feedthrough (note 6) 5 nv-s digital crosstalk (note 7) 5 nv-s digital-to-analog glitch impulse major carry transition 120 nv-s dac-to-dac crosstalk (note 8) 15 nv-s output noise spectral density at 1khz full-scale code 250 nv/ hz analog outputs (out0 to out31) output voltage range v ss = -0.5v, av cc = +5v 0 5 v resistive load to ground 10 50 k ?
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface _______________________________________________________________________________________ 3 electrical characteristics?ax5732 (0 to +5v output voltage range) (continued) (av cc = +5.25v to +5.5v (note 1), av dd = +5v ?%, dv dd = +2.7v to av dd , v ss = agnd = dgnd = refgnd = gs = 0, v ref = +3.0v, r l = , c l = 50pf referenced to ground, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units capacitive load to ground 50 100 pf dc output impedance 0.1 ? sourcing, full-scale code, output connected to agnd 5 short-circuit current sinking, zero-scale code, output connected to av cc -5 ma ground-sense analog input (gs) input voltage range v gs relative to agnd -0.5 +0.5 v gs gain a gs 0.995 1.000 1.005 v/v input resistance -0.5v v gs +0.5v, v ss = -0.5v 35 k ? reference input (ref) input resistance 1m ? reference input voltage range v ref referred to refgnd 2.900 3.000 3.100 v digital inputs ( cs , sclk, din, ldac , clr , dsp ) dv dd = +2.7v to +3.6v 0.7 dv dd input-voltage high v ih dv dd = +4.75v to +5.25v 2.4 v input-voltage low v il 0.8 v input capacitance c in 10 pf input current i in digital inputs = 0 or dv dd ? ? power requirements (av cc , v ss , agnd, av dd , dv dd , dgnd) output-amplifier positive supply voltage av cc 4.75 5.50 v output-amplifier negative supply voltage v ss -0.5 0v output-amplifier supply voltage difference av cc - v ss 5.75 v analog supply voltage av dd 4.75 5.25 v digital supply voltage dv dd 2.70 5.25 v v out0 through v out31 = 0 10 15 ma analog supply current ai dd software shutdown 10 ? v ih = dv dd , v il = 0, f sclk = 20mhz 2.5 3.5 digital supply current di dd v ih = +2.4v, v il = +0.8v, f sclk = 20mhz 5 6.5 ma v out0 through v out31 = 0 4 10 ma output-amplifier positive supply current ai cc software shutdown 20 ? v out0 through v out31 = 0 -4 -10 ma output-amplifier negative supply current i ss v ss = -0.5v software shutdown -20 ? power-supply rejection ratio psrr -95 db
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface 4 _______________________________________________________________________________________ electrical characteristics?ax5733 (0 to +10v output voltage range) (av cc = +10.5v to +11v, av dd = 5v ?%, dv dd = +2.7v to av dd , v ss = agnd = dgnd = refgnd = gs = 0, v ref = +3.0v, r l = , c l = 50pf referenced to ground, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units dc characteristics resolution n 16 bits MAX5733b ? ?6 integral nonlinearity (note 2) inl MAX5733c ?2 ?4 lsb differential nonlinearity dnl guaranteed monotonic (note 3) ? lsb zero-scale error v os v ss = -0.5v, av cc = +10v (note 4) ? ?0 mv full-scale error (note 4) ? ?0 mv gain error ?.1 ?.5 % fsr gain temperature coefficient 20 ppm fsr/? dc crosstalk v ss = -0.5v, av cc = +10v (note 5) 50 250 ? dynamic characteristics output-voltage settling time full-scale change to ?.5 lsb 20 ? voltage-output slew rate 1 v/? digital feedthrough (note 6) 5 nv-s digital crosstalk (note 7) 5 nv-s digital-to-analog glitch impulse major carry transition 120 nv-s dac-to-dac crosstalk (note 8) 15 nv-s output noise spectral density at 1khz full-scale code 250 nv/ hz analog outputs (out0 to out31) output voltage range v ss = -0.5v, av cc = +10.5v 0 10 v resistive load to ground 10 50 k ? capacitive load to ground 50 100 pf dc output impedance 0.1 ? sourcing, full scale, output connected to agnd 5 short-circuit current sinking, zero scale, output connected to av cc -5 ma ground-sense analog input (gs) input voltage range v gs relative to agnd -0.5 +0.5 v gs gain a gs 0.995 1.000 1.005 v/v input resistance -0.5v v gs +0.5v, v ss = -0.5v 70 k ? reference input (ref) input resistance 1m ? reference input voltage range v ref referred to refgnd 2.900 3.000 3.100 v
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface _______________________________________________________________________________________ 5 electrical characteristics?ax5733 (0 to +10v output voltage range) (continued) (av cc = +10.5v to +11v, av dd = 5v ?%, dv dd = +2.7v to av dd , v ss = agnd = dgnd = refgnd = gs = 0, v ref = +3.0v, r l = , c l = 50pf referenced to ground, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units digital inputs ( cs , sclk, din, ldac , clr , dsp ) dv dd = +2.7v to +3.6v 0.7 dv dd input-voltage high v ih dv dd = +4.75v to +5.25v 2.4 v input-voltage low v il 0.8 v input capacitance c in 10 pf input current i in digital inputs = 0 or dv dd ? ? power requirements (av cc , v ss , agnd, av dd , dv dd , dgnd) output-amplifier positive supply voltage av cc 10 11 v output-amplifier negative supply voltage v ss -0.5 0 v output-amplifier supply voltage difference av cc - v ss 11 v analog supply voltage av dd 4.75 5.25 v digital supply voltage dv dd 2.70 5.25 v v out0 through v out31 = 0 10 15 ma analog supply current ai dd software shutdown 10 ? v ih = dv dd , v il = 0, f sclk = 20mhz 2.5 3.5 digital supply current di dd v ih = +2.4v, v il = +0.8v, f sclk = 20mhz 5 6.5 ma v out0 through v out31 = 0 4 10 ma output-amplifier positive supply current ai cc software shutdown 20 ? v out0 through v out31 = 0 -4 -10 ma output-amplifier negative supply current i ss v ss = -0.5v software shutdown -20 ? power-supply rejection ratio psrr -95 db
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface 6 _______________________________________________________________________________________ electrical characteristics?ax5734 (-2.5v to +7.5v output voltage range) (av cc = +7.75v to +8.25v, av dd = +5v ?%, dv dd = +2.7v to av dd , v ss = -2.75v to -3.25v, agnd = dgnd = refgnd = gs = 0, program the offset dac to 4000hex. v ref = +3.0v, r l = , c l = 50pf referenced to ground, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units dc characteristics resolution n 16 bits max5734b ? ?6 integral nonlinearity (note 2) inl max5734c ?2 ?4 lsb differential nonlinearity dnl guaranteed monotonic (note 3) ? lsb zero-scale error v os v ss = -3.25v, av cc = +7.75v (note 4) ? ?0 mv full-scale error (note 4) ? ?0 mv gain error ?.1 ?.5 %fsr gain temperature coefficient 20 ppm fsr/? dc crosstalk v ss = -3.25v, av cc = +7.75v (note 4) 50 250 ? dynamic characteristics output-voltage settling time full-scale change to ?.5 lsb 20 ? voltage-output slew rate 1 v/? digital feedthrough (note 6) 5 nv-s digital crosstalk (note 7) 5 nv-s digital-to-analog glitch impulse major carry transition 120 nv-s dac-to-dac crosstalk (note 8) 15 nv-s output noise spectral density at 1khz full-scale code 250 nv/ hz analog outputs (out0 to out31) output voltage range v ss = -2.75v, av cc = +7.75v -2.5 +7.5 v resistive load to ground 10 50 k ? capacitive load to ground 50 100 pf dc output impedance 0.1 ? sourcing, full scale, output connected to agnd 5 short-circuit current sinking, zero scale, output connected to av cc -5 ma ground-sense analog input (gs) input voltage range v gs relative to agnd -0.5 +0.5 v gs gain a gs 0.995 1.000 1.005 v/v input resistance -0.5v v gs +0.5v, v ss = -0.5v 70 k ? reference input (ref) input resistance 1m ? reference input voltage range v ref referred to refgnd 2.900 3.000 3.100 v
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface _______________________________________________________________________________________ 7 electrical characteristics?ax5734 (-2.5v to +7.5v output voltage range) (continued) (av cc = +7.75v to +8.25v, av dd = +5v ?%, dv dd = +2.7v to av dd , v ss = -2.75v to -3.25v, agnd = dgnd = refgnd = gs = 0, program the offset dac to 4000hex. v ref = +3.0v, r l = , c l = 50pf referenced to ground, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units digital inputs ( cs , sclk, din, ldac , clr , dsp ) dv dd = +2.7v to +3.6v 0.7 dv dd input-voltage high v ih dv dd = +4.75v to +5.25v 2.4 v input-voltage low v il 0.8 v input capacitance c in 10 pf input current i in digital inputs = 0 or dv dd ? ? power requirements (av cc , v ss , agnd, av dd , dv dd , dgnd) output-amplifier positive supply voltage av cc 7.50 8.25 v output-amplifier negative supply voltage v ss -3.25 -2.50 v output-amplifier supply voltage difference av cc - v ss 11 v analog supply voltage av dd 4.75 5.25 v digital supply voltage dv dd 2.70 5.25 v v out0 through v out31 = 0 10 15 ma analog supply current ai dd software shutdown 10 ? v ih = dv dd , v il = 0, f sclk = 20mhz 2.5 3.5 digital supply current di dd v ih = +2.4v, v il = +0.8v, f sclk = 20mhz 5 6.5 ma v out0 through v out31 = 0 4 10 ma output-amplifier positive supply current ai cc software shutdown 20 ? v out0 through v out31 = 0 -4 -10 ma output-amplifier negative supply current i ss v ss = -2.75v software shutdown -20 ? power-supply rejection ratio psrr -95 db
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface 8 _______________________________________________________________________________________ electrical characteristics?ax5735 (-5v to +5v output voltage range) (av cc = +5.25v to +5.5v, av dd = +5v ?%, dv dd = +2.7v to av dd , v ss = -5.25v to -5.5v, agnd = dgnd = refgnd = gs = 0, program the offset dac to 8000hex. v ref = +3.0v, r l = , c l = 50pf referenced to ground, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units dc characteristics resolution n 16 bits max5735b ? ?6 integral nonlinearity (note 2) inl max5735c ?2 ?4 lsb differential nonlinearity dnl guaranteed monotonic (note 3) ? lsb zero-scale error v os v ss = -5.25v, av cc = +5.25v (note 4) ? ?0 mv full-scale error (note 4) ? ?0 mv gain error ?.1 ?.5 %fsr gain temperature coefficient 20 ppm fsr/? dc crosstalk v ss = -5.75v, av cc = +5.25v (note 5) 50 250 ? dynamic characteristics output-voltage settling time full-scale change to ?.5 lsb 20 ? voltage-output slew rate 1 v/? digital feedthrough (note 6) 5 nv-s digital crosstalk (note 7) 5 nv-s digital-to-analog glitch impulse major carry transition 120 nv-s dac-to-dac crosstalk (note 8) 15 nv-s output noise spectral density at 1khz full-scale code 250 nv/ hz analog outputs (out0 through out31) output voltage range v ss = -5.25v, av cc = +5.25v -5 +5 v resistive load to ground 10 50 k ? capacitive load to ground 50 100 pf dc output impedance 0.1 ? sourcing, full scale, output connected to agnd 5 short-circuit current sinking, zero scale, output connected to av cc -5 ma ground-sense analog input (gs) input voltage range v gs relative to agnd -0.5 +0.5 v gs gain a gs 0.995 1.000 1.005 v/v input resistance -0.5v v gs +0.5v, v ss = -0.5v 70 k ? reference input (ref) input resistance 1m ? reference input voltage range v ref referred to refgnd 2.900 3.000 3.100 v
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface _______________________________________________________________________________________ 9 electrical characteristics?ax5735 (-5v to +5v output voltage range) (continued) (av cc = +5.25v to +5.5v, av dd = +5v ?%, dv dd = +2.7v to av dd , v ss = -5.25v to -5.5v, agnd = dgnd = refgnd = gs = 0, program the offset dac to 8000hex. v ref = +3.0v, r l = , c l = 50pf referenced to ground, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units digital inputs ( cs , sclk, din, ldac , clr , dsp ) dv dd = +2.7v to +3.6v 0.7 dv dd input-voltage high v ih dv dd = +4.75v to 5.25v 2.4 v input-voltage low v il 0.8 v input capacitance c in 10 pf input current i in digital inputs = 0 or dv dd ? ? power requirements (av cc , v ss , agnd, av dd , dv dd , dgnd) output-amplifier positive supply voltage av cc 4.75 5.50 v output-amplifier negative supply voltage v ss -5.50 -4.75 v output-amplifier supply voltage difference av cc - v ss 11 v analog supply voltage av dd 4.75 5.25 v digital supply voltage dv dd 2.70 5.25 v v out0 through v out31 = 0 10 15 ma analog supply current ai dd software shutdown 10 ? v ih = dv dd , v il = 0, f sclk = 20mhz 2.5 3.5 digital supply current di dd v ih = +2.4v, v il = +0.8v, f sclk = 20mhz 5 6.5 ma v out0 through v out31 = 0 4 10 ma output-amplifier positive supply current ai cc software shutdown 20 ? v out0 through v out31 = 0 -4 -10 ma output-amplifier negative supply current i ss v ss = -0.5v software shutdown -20 ? power-supply rejection ratio psrr -95 db note 1: av cc should be at least 0.25v higher than the maximum output voltage required from the dac. full-scale output is 5v for the max5732. note 2: linearity guaranteed from code 2047 to full scale and from (v ss + 0.3v) to (av cc - 0.3v). note 3: dnl guaranteed over all codes for (v ss + 0.3v) to (av cc - 0.3v). note 4: zero-scale error is measured at code 0. full-scale error is measured at code ffffhex. note 5: dc crosstalk is the change in the output level of one dac at midscale in response to the full-scale output change of all other dacs. note 6: digital feedthrough is a measure of the impulse injected into the analog outputs from the digital control inputs when the device is not being written to. it is measured with a worst-case change on the digital inputs. note 7: digital crosstalk is the glitch impulse transferred to the output of one dac at midscale while a full-scale code change is writ ten into another dac. note 8: dac-to-dac crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog output change at another converter.
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface 10 ______________________________________________________________________________________ timing characteristicsdv dd = +2.7v to +5.25v (figures 2 and 3, av dd = +4.75v to +5.25v, dv dd = +2.7v to +5.25v, agnd = dgnd = refgnd = gs = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units serial clock frequency f sclk 0 25 mhz sclk pulse-width high t ch 10 ns sclk pulse-width low t cl 10 ns sclk fall to cs fall setup time t scs 10 ns cs fall to sclk fall setup time t css 10 ns cs rise to sclk fall t cs1 at end of cycle in spi mode only 18 ns sclk fall to cs rise setup time t cs2 0ns din to sclk fall setup time t ds 10 ns din to sclk fall hold time t dh 2ns sclk fall to dout fall t scl load capacitance = 20pf 25 ns sclk fall to dout rise t sdh load capacitance = 20pf 25 ns cs pulse-width high t cspwh 50 ns cs pulse-width low t cspwl 20 ns ldac pulse-width low t ldac 20 ns clr pulse-width low t clr 20 ns timing characteristicsdv dd = +4.75v to +5.25v (figures 2 and 3, av dd = +4.75v to +5.25v, dv dd = +4.75v to +5.25v, agnd = dgnd = refgnd = gs = 0, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units serial clock frequency f sclk 033mhz sclk pulse-width high t ch 10 ns sclk pulse-width low t cl 10 ns sclk fall to cs fall setup time t scs 6ns cs fall to sclk fall setup time t css 5ns cs rise to sclk fall t cs1 at end of cycle in spi mode only 15 ns sclk fall to cs rise setup time t cs2 0ns din to sclk fall setup time t ds 10 ns din to sclk fall hold time t dh 2ns sclk fall to dout fall t scl load capacitance = 20pf 20 ns sclk fall to dout rise t sdh load capacitance = 20pf 20 ns cs pulse-width high t cspwh 50 ns cs pulse-width low t cspwl 20 ns ldac pulse-width low t ldac 20 ns clr pulse-width low t clr 20 ns
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface ______________________________________________________________________________________ 11 worst-case dnl vs. temperature max5732 toc04 temperature ( c) dnl (lsb) 60 35 10 -15 0.05 0.10 0.15 0.20 0.25 0 -40 85 zero-scale error vs. temperature max5732 toc05 temperature ( c) zero-scale error (mv) 60 35 10 -15 1 2 3 4 5 6 0 -40 85 v ss = -0.5v full-scale error vs. temperature max5732 toc06 temperature ( c) full-scale error (mv) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 -40 85 analog supply current vs. temperature max5732 toc07 temperature ( c) av dd (ma) 60 35 10 -15 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9.0 8.0 -40 85 digital supply current vs. temperature max5732 toc08 temperature ( c) dv dd ( a) 60 35 10 -15 51 52 53 54 55 56 57 58 59 60 50 -40 85 dv dd = +3v all digital inputs at zero or dv dd digital supply current vs. temperature max5732 toc09 temperature ( c) dv dd ( a) 60 35 10 -15 102 103 104 105 106 107 108 109 110 111 101 -40 85 dv dd = +5v all digital inputs at zero or dv dd typical operating characteristics (av cc = +10.5v ?%, av dd = +5v ?%, dv dd = +5v, v ss = agnd = dgnd = refgnd = gs = 0, v ref = +3.000v, r l = , c l = 50pf referenced to ground, output gain = 2.5, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?). integral nonlinearity vs. input code max5732 toc01 input code inl (lsb) 60k 50k 40k 30k 20k 10k 0 1 2 3 4 5 -1 070k differential nonlinearity vs. input code max5732 toc02 input code dnl (lsb) 60k 50k 40k 30k 20k 10k -0.1 0 0.1 0.2 0.3 0.4 -0.2 070k worst-case inl vs. temperature max5732 toc03 temperature ( c) inl (lsb) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 0 -40 85
typical operating characteristics (continued) (av cc = +10.5v ?%, av dd = +5v ?%, dv dd = +5v, v ss = agnd = dgnd = refgnd = gs = 0, v ref = +3.000v, r l = , c l = 50pf referenced to ground, output gain = 2.5, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?). max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface 12 ______________________________________________________________________________________ large-signal step response (low to high) max5732 toc11 2 s/div cs 5v/div out_ 5v/div large-signal step response (high to low) max5732 toc12 2 s/div cs 5v/div out_ 5v/div noise voltage density max5732 toc13 frequency (mhz) noise (nv/ hz ) 3.0 3.5 4.0 4.5 2.5 2.0 1.5 1.0 0.5 100 10 1000 1 0 5.0 major carry transition (7fffhex to 8000hex) max5732 toc14 1 s/div out_ 20mv/div cs 5v/div major carry transition (8000hex to 7fffhex) max5732 toc15 1 s/div cs 5v/div out_ 20mv/div digital feedthrough max5732 toc10 400ns/div sclk 5v/div out_ 10mv/div
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface ______________________________________________________________________________________ 13 pin name function 1, 42, 48 av cc output-amplifier positive supply input. bypass to v ss with a 0.1? capacitor. 2 out9 dac9 buffered analog output voltage 3 out8 dac8 buffered analog output voltage 4 out7 dac7 buffered analog output voltage 5 n.c. no connection. internally connected. do not make any connections to n.c. 6 out6 dac6 buffered analog output voltage 7 out5 dac5 buffered analog output voltage 8 out4 dac4 buffered analog output voltage 9, 38 agnd analog ground 10 out3 dac3 buffered analog output voltage 11, 28, 39 v ss output-amplifier negative supply input 12 out2 dac2 buffered analog output voltage 13 out1 dac1 buffered analog output voltage 14 out0 dac0 buffered analog output voltage 15 dsp digital serial-interface-select input. drive low for dsp-interface mode. drive high for spi-interface mode. 16 cs active-low digital chip-select input 17 dout digital serial-data output. use dout to daisy chain and read the contents of the dac registers. 18 sclk digital serial-clock input 19 din digital serial-data input 20 dv dd digital power-supply input. bypass to dgnd with a 0.1? capacitor. 21 dgnd digital ground 22 ldac active-low digital load dac input. drive this asynchronous input low to transfer the contents of the input register to their respective dac registers and set all dac outputs accordingly. 23 clr active-low digital clear input. drive this asynchronous input low to clear the contents of the input and dac registers and set all the dac outputs to zero. 24 gs ground-sense analog input. offsets the dac amplifier outputs by ?.5v to compensate for a remote system ground potential difference. 25, 49 refgnd reference ground 26 ref analog reference voltage input 27, 50 av dd analog power-supply input. bypass to agnd with a 0.1? capacitor. 29 out31 dac31 buffered analog output voltage 30 out30 dac30 buffered analog output voltage 31 out29 dac29 buffered analog output voltage 32 out28 dac28 buffered analog output voltage 33 out27 dac27 buffered analog output voltage 34 out26 dac26 buffered analog output voltage 35 out25 dac25 buffered analog output voltage 36 out24 dac24 buffered analog output voltage 37 out23 dac23 buffered analog output voltage pin description
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface 14 ______________________________________________________________________________________ pin name function 40 out22 dac22 buffered analog output voltage 41 out21 dac21 buffered analog output voltage 43 out20 dac20 buffered analog output voltage 44 out19 dac19 buffered analog output voltage 45 out18 dac18 buffered analog output voltage 46 out17 dac17 buffered analog output voltage 47 out16 dac16 buffered analog output voltage 51 out15 dac15 buffered analog output voltage 52 out14 dac14 buffered analog output voltage 53 out13 dac13 buffered analog output voltage 54 out12 dac12 buffered analog output voltage 55 out11 dac11 buffered analog output voltage 56 out10 dac10 buffered analog output voltage ?p exposed paddle. internally connected to v ss . connect externally to a metal pad for improved thermal dissipation. pin description (continued)
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface ______________________________________________________________________________________ 15 av dd v ss agnd dv dd dgnd av cc input register offset dac dsp cs sclk ref offset dac register gs input register dac31 register dac31 input register dac30 register dac30 out30 out31 av cc av cc av cc v ss v ss v ss av cc v ss av cc v ss input register dac1 register dac1 out1 input register dac0 register dac0 out0 power management input register dac_ register dac_ out_ dout ldac clr din digital control logic refgnd max5732 MAX5733 max5734 max5735 figure 1. functional diagram
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface 16 ______________________________________________________________________________________ detailed description the max5732?ax5735 are 32-channel, 16-bit, volt- age-output dacs (figure 1). the devices accept a 3v external reference input at ref. an internal offset dac allows all outputs to be offset (see table 1). the devices provide a ground-sensing function that allows the output voltages to be referenced to a remote ground. a 33mhz spi-/qspi/-microwire- and dsp-compatible serial interface controls the max5732?ax5735 (figure 2). each dac includes a double-buffered input structure to minimize the digital noise feedthrough from the digital inputs to the outputs, and allows for synchronous or asynchronous updating of the outputs. the two buffers are organized as an input register followed by a dac register that stores the contents of the output. input reg- isters update the dac registers independently or simul- taneously with a single software or hardware command. the max5732?ax5735 also have a dout that allows for read-back or daisy chaining multiple devices. the max5732?ax5735 analog and digital sections have separate power inputs. separate power inputs are also provided for the output buffer amplifiers. proprietary deglitch circuits prevent output glitches at power-up and eliminate the need for power sequenc- ing. a software-shutdown mode allows efficient power management. the max5732?ax5735 consume 50? of supply current in shutdown. all dacs provide buffered outputs that can drive 10k ? in parallel with 100pf. the max5732 has a 0 to +5v output range; the MAX5733 has a 0 to +10v output range; the max5734 has a -2.5v to +7.5v output range; and the max5735 has a -5v to +5v output range. the max5732?ax5735 are available in a 56-pin 8mm x 8mm thin qfn package and are specified over the extended -40? to +85? temperature range. external reference input (ref) the ref voltage sets the full-scale output voltage for all 32 dacs. ref accepts a +3v ?% input. reference voltages outside these limits can result in a degradation of device performance. ref is a buffered input. the typical input impedance is 10m ? , and it does not vary with code. use a high- accuracy, low-noise voltage reference such as the max6126aasa30 (3ppm/? temp drift and 0.02% initial accuracy) to improve static accuracy. ref does not accept ac signals. ground sense (gs) the max5732?ax5735 include a gs that allows the output voltages to be referenced to a remote ground. the gs input voltage range (v gs ) is -0.5v to +0.5v. v gs is added to the output voltage with unity gain. the resulting output voltage must be within the valid output- voltage range set by the power supplies. see the output amplifiers (out0?ut31) section for the effect of the gs inputs on the dac outputs. offset dac the max5732?ax5735 feature an offset dac that determines the output voltage range. while each part number has an output voltage range associated with it, sclk xx 1 2 3 32 x din d0 c0 c1 c2 t cl t ch t dh t ds t cs2 t cs1 t css t scs t cspwl t cspwh cs (dsp mode) cs ( c mode) figure 2. serial-interface timing
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface ______________________________________________________________________________________ 17 it is the offset dac that determines the end-point volt- ages of the range. table 1 shows the offset dac code required during power-up. note: the offset dac of every device can be pro- grammed with any of the four output voltage ranges. however, the specifications in the electrical characteristics table are only guaranteed (production tested) for the offset code associated with each partic- ular part number. for example, the max5734 specifica- tions are only valid with the max5734 offset- dac code shown in table 1. the offset dac is summed with gs (figure 1). the offset dac can also cancel the offset of the output buffers. any change in the offset dac affects all 32 dacs. the offset dac is also configured identically to the other 32 dacs with an input and dac register. write to the offset dac through the serial interface by using control bits c2, c1, and c0 = 001 followed by the data bits d15?0. the clr command affects the offset dac as well as the other dacs. the data format for the offset dac codes are: control bits c2, c1, and c0 = 011, address bits a5?0 = 100000, 7 don?-care bits, and 16 data bits as shown in table 2. output amplifiers (out0?ut31) all dac outputs are internally buffered. the internal buffers provide gain, improved load regulation, and tran- sition glitch suppression for the dac outputs. the output buffers slew at 1v/? and can drive 10k ? in parallel with 100pf. the output buffers are powered by av cc and v ss . av cc and v ss determine the maximum output voltage range of the device. the input code, the voltage reference, the offset dac output, the voltage on gs, and the gain of the output amplifier determine the output voltage. calculate v out as follows: where gain = 5/3 for the max5732, or gain = 10/3 for the MAX5733/max5734/max5735. load-dac ( ldac ) input the max5732?ax5735 feature an active-low ldac logic input that allows the outputs out_ to update asynchronously. keep ldac high during normal opera- tion (when the device is controlled only through the ser- ial interface). drive ldac low to simultaneously update all dac outputs with data from their respective input registers. figure 3 shows the ldac timing with respect to out_. v gain v dac code offset dac code v out ref gs = () + ? 2 16 part number d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 max5732 0000000000000000 MAX5733 0000000000000000 max5734 0100000000000000 max5735 1000000000000000 table 1. offset dac codes out_ 0.5 lsb t s t ldac ldac figure 3. ldac timing note: for the max5732, the maximum code for the offset dac is 16384. for the MAX5733/max5734/max5735, the maximum code for the offset dac is 40000. table 2. serial data format control bits address bits don?- care bits data bits c2, c1, and c0 a5?0 d15?0 011 100000 xxxxxxx see table 1
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface 18 ______________________________________________________________________________________ a software command can also activate the ldac oper- ation. to activate ldac by software, set control bits c2, c1, and c0 = 010, address bits a5?0 = 111111, and all data bits to don? care. see table 3 for the data format. this operation updates all dac outputs. note: the software load dac does not affect the offset dac. clear ( clr ) the max5732?ax5735 feature an active-low clr logic input that sets all channels including the offset dac to 0v (code 0000hex). the offset dac needs to be reprogrammed after clr is asserted. driving clr low clears the contents of both the input and dac registers. the serial interface can also issue a software clear com- mand. setting the control bits c2, c1, and c0 = 111 (table 4) performs the same function as driving logic- input clr low. table 4 shows the clear-data format for the software-controlled clear command. this register- reset process cannot be interrupted. all serial input data is ignored until the entire reset process is complete. serial interface a 3-wire spi-/qspi-/microwire- and dsp-compatible serial interface controls the max5732?ax5735. the interface requires a 32-bit command word to control the device. the command word consists of 3 control bits, 6 address bits, 7 don?-care bits, and 16 data bits. table 5 shows the general serial-data format. the control bits control various write and read commands as well as the load dac and clear commands. table 6 shows the con- trol-bit functions. the address bits select the register(s) to be written. table 7 shows the address functions. the data bits control the value of the dac outputs. table 3. load-dac data format control bits address bits don?- care bits data bits c2, c1, and c0 a5?0 d15?0 010 111111 xxxxxxx xxxxxxxxxxxxxxxx table 4. clear-data format control bits address bits dont- care bits data bits c2, c1, and c0 a5?0 d15?0 111 see table 7 xxxxxxx xxxxxxxxxxxxxxxx table 5. serial-data format control bits address bits don?- care bits data bits msb lsb c2, c1, and c0 a5?0 xxxxxxx d15?0 table 6. control-bit functions control bits c2 c1 c0 control-bit description 000 no operation (nop); no internal registers change state. the nop command can be passed to dout depending on the state of the configuration register. address bits a5?0 and data bits d15?0 are ignored. 001 loads d15?0 into the input register(s) for the selected address. depending on the address bits, this command could write to: the configuration register (a[5:0] = 100001) one of the i np ut r eg i ster s of the 32 d ac channel s all 32 dac input registers (a[5:0] = 111111) the offset d ac i np ut r eg i ster ( a[ 5:0] = 100000) 010 loads dac register(s) from the input register(s). depending on the address bits, this command can update one or all of the dac registers from the stored input register value(s). data bits d15?0 are ignored. 011 write-through; loads d15?0 into the input and dac registers, depending on the address bits. 100 read command; depending on the address bits, one of the dac-register values or the configuration-register value may be read back through dout. data bits d15?0 are ignored. 1 0 1 reserved for internal testing; do not use. 1 1 0 reserved for internal testing; do not use. 111 c l ear r eg i ster ( s) ; d ep end i ng on the ad d r ess b i ts, one or al l r eg i ster s ( excep t the offset- d ac r eg i ster s) ar e cl ear ed to zer o. d ata b i ts d 15d 0 ar e i g nor ed .
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface ______________________________________________________________________________________ 19 table 7. address-bit functions address bits a5 a4 a3 a2 a1 a0 control function 0 0 0 0 0 0 dac0 0 0 0 0 0 1 dac1 0 0 0 0 1 0 dac2 0 0 0 0 1 1 dac3 0 0 0 1 0 0 dac4 0 0 0 1 0 1 dac5 0 0 0 1 1 0 dac6 0 0 0 1 1 1 dac7 0 0 1 0 0 0 dac8 0 0 1 0 0 1 dac9 0 0 1 0 1 0 dac10 0 0 1 0 1 1 dac11 0 0 1 1 0 0 dac12 0 0 1 1 0 1 dac13 0 0 1 1 1 0 dac14 0 0 1 1 1 1 dac15 0 1 0 0 0 0 dac16 0 1 0 0 0 1 dac17 0 1 0 0 1 0 dac18 0 1 0 0 1 1 dac19 0 1 0 1 0 0 dac20 0 1 0 1 0 1 dac21 0 1 0 1 1 0 dac22 0 1 0 1 1 1 dac23 0 1 1 0 0 0 dac24 0 1 1 0 0 1 dac25 0 1 1 0 1 0 dac26 0 1 1 0 1 1 dac27 0 1 1 1 0 0 dac28 0 1 1 1 0 1 dac29 0 1 1 1 1 0 dac30 0 1 1 1 1 1 dac31 1 0 0 0 0 0 offset dac 100001 c onfi g ur ati on r eg i ster ; contr ol b i ts c 2, c 1, and c 0 = 010 and c 2, c 1, and c 0 = 011 set the er r or fl ag i n the confi g ur ati on r eg i ster . d o not use these contr ol b i ts w i th these ad d r ess b i ts. address bits a5 a4 a3 a2 a1 a0 control function 100010c om m and r eser ved ; d o not use. 100011c om m and r eser ved ; d o not use. 100100c om m and r eser ved ; d o not use. 100101c om m and r eser ved ; d o not use. 100110c om m and r eser ved ; d o not use. 100111c om m and r eser ved ; d o not use. 101000c om m and r eser ved ; d o not use. 101001c om m and r eser ved ; d o not use. 101010c om m and r eser ved ; d o not use. 101011c om m and r eser ved ; d o not use. 101100c om m and r eser ved ; d o not use. 101101c om m and r eser ved ; d o not use. 101110c om m and r eser ved ; d o not use. 101111c om m and r eser ved ; d o not use. 110000c om m and r eser ved ; d o not use. 110001c om m and r eser ved ; d o not use. 110010c om m and r eser ved ; d o not use. 110011c om m and r eser ved ; d o not use. 110100c om m and r eser ved ; d o not use. 110101c om m and r eser ved ; d o not use. 110110c om m and r eser ved ; d o not use. 110111c om m and r eser ved ; d o not use. 111000c om m and r eser ved ; d o not use. 111001c om m and r eser ved ; d o not use. 111010c om m and r eser ved ; d o not use. 111011c om m and r eser ved ; d o not use. 111100c om m and r eser ved ; d o not use. 111101c om m and r eser ved ; d o not use. 111110c om m and r eser ved ; d o not use. 111111 all channels (dac31?ac0); used for write commands only. read commands cannot be used with these address bits.
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface 20 ______________________________________________________________________________________ dsp mode ( dsp ) the max5732?ax5735 provide a hardware-selectable dsp-interface mode. dsp mode, when active, allows chip select ( cs ) to go high before the entire 32-bit com- mand word is clocked in. the active-low dsp logic input selects microcontroller (?)- or dsp-interface mode. drive dsp low for dsp-interface mode. drive dsp high for ?-interface mode. figure 2 illustrates serial timing for both ?- and dsp-interface modes. configuration register the configuration register controls the advanced fea- tures of the max5732?ax5735. write to the configura- tion register by setting the control bits c2, c1, and c0 = 001 and address bits a5?0 = 100001. table 8 shows the configuration-register data format for the d15?0 data bits. table 9 shows the commands con- trolled by the configuration register. table 9. configuration-register commands data bit name description d15 errf error flag; errf goes logic-high when an invalid command is attempted. errf is cleared each time the configuration register is read back to dout. clear-register commands c2, c1, and c0 = 111 resets errf. conditions that trigger errf include: attempted read of address bits a5?0 = 111111 (all 32 dacs) access to reserved addresses access to the configuration register (address bits a5?0 = 100001 when used with control bits c2, c1, and c0 = 010 and 011) default is logic-low (no error flags); errf is read only. d14 sing single device; sing determines the manner in which data is output to dout. a logic-high sets the device to operate in stand-alone mode or in parallel; only the 16 data bits are output to dout. a logic-low sets the device to operate in a daisy chain of devices. in this case, the entire 32-bit command word is output to dout. default is logic-low (daisy-chain mode); sing is read/write. d13 glt glitch-suppression enable; the max5732?ax5735 feature glitch-suppression circuitry on the analog outputs that minimizes the output glitch during a major carry transition. a logic-low disables the internal glitch-suppression circuitry, which improves settling time. a logic-high enables glitch- suppression, suppressing up to 120nv-s glitch impulse on the dac outputs. default is logic-low (glitch suppression disabled); glt is read/write. d12 dt digital output enable; a logic-low enables dout. a logic-high disables dout. disabling dout reduces power consumption and digital noise feedthrough to the dac outputs from the dout output buffer. default is logic-low (dout enabled); dt is read/write. d11 shdn shutdown; a logic-high shuts down all 32 dacs. the logic interface remains active, and the data is retained in the input and dac registers. read/write operations can be performed while the device is disabled; however, no changes can occur at the device outputs. a logic-low powers up all 32 dacs if the device was previously in shutdown. upon waking up, the dac outputs return to the last stored value in the dac registers. default is logic-low (normal operation); shdn is read/write. d10?0 x don? care. table 8. configuration-register data format 16 data bits d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 errf sing glt dt shdn xxxxxxxxxxx x = don? care.
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface ______________________________________________________________________________________ 21 sing when sing = 0 (default power-up mode), the device is in daisy-chain mode. dout follows din after 32 clock cycles. for the read command, dout provides the read data in the next cycle following cs rising edge. the 16 data bits of the previous command word are clocked out on the last 16 clock cycles of the current command word. when sing = 1, the device is in stand-alone mode. to reduce the time it takes to read data out, the read data is provided at dout as the 16 data bits of the current com- mand are clocked in. the device acts on an incoming command word independent of the rising edge of cs . daisy chain operation any number of the max5732?ax5735 devices can be daisy chained by connecting the dout of one device to the din of another device in a chain. all devices must be in sing = 0 mode. connecting the cs inputs of all devices together eliminates the need to issue nop com- mands to devices early in the chain (see figure 4). data readback the contents of the max5732?ax5735 dac and con- figuration registers can be read on dout by issuing a read-data command. setting control bits c2, c1, and c0 = 100, puts the device in read-data mode. the address bits select the register to be read. the con- tents of the register (16 data bits) are clocked out at dout. the output-data format depends on the status of dsp and sing. table 10 shows the manner in which data is written to dout. note that when the device is in dsp mode ( dsp = 0), only the 16-bit data of the selected register is written to dout. table 10. read-data modes with sing and dsp controls dsp sing configuration description read data at dout 0 0 stand alone dout provides the 16 data bits from the previous command word. data appears at dout on the last 16 clock edges of the current command word. see figure 7. 0 1 stand alone d ou t p r ovi d es the 16 d ata b i ts fr om the cur r ent com m and w or d . d ata ap p ear s at d ou t on the l ast 16 cl ock ed g es of the cur r ent com m and w or d . s ee fi g ur e 7. 1 0 daisy chain data on dout follows the current command word after 32 clock cycles. for read commands, the read data from the previous command word appears at dout on the last 16 clock edges of the current command word. see figure 4. 11 multiple douts connected in parallel (not daisy chained) dout provides the 16 data bits from the current command word. data appears at dout on the last 16 clock edges of the current command word. for read commands, the read data from the current command word appears at dout on the last 16 clock edges of the current command word. see figures 8 and 9. controller device din(0) dout(0) 1 sclk cs dsp max573_ din(1) dout(1) sclk cs dsp max573_ din(2) dout(2) sclk cs dsp max573_ figure 4. daisy-chain configuration
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface 22 ______________________________________________________________________________________ w wd2 w wd1 w wd0 r xx r xx r xx x xx x xx x xx din(0) cs dout(0) wd1 w wd2 wxx r xx r wd0 w r rd0 x xx x xx dout(1) w wd2 w wd1 w wd0 r xx r rd1 r rd0 x xx dout(2) w wd2 w wd1 w wd0 r rd2 r rd1 r rd0 w wd2 r xx w wd0 r xx w wd1 r xx x xx x xx x xx din(0) cs dout(0) xx r wd2 w wd1 w xx r wd0 w r rd0 x xx x xx dout(1) w wd2 r rd1 w wd0 r xx w wd1 r rd0 x xx dout(2) w wd2 r rd1 w wd0 r rd2 w wd1 r rd0 figure 5. example 1 of a daisy-chain data sequence w/wd0 = 32-bit word with a write command; wd0 writes data for device 0. the 0 refers to the position in the daisy chain (0 is c losest to the bus master). devices 1 and 2 are devices further down the chain. r/rd2 = 32-bit word with a read command; rd2 reads data from device 2. x = don? care (for x in the data or command position). figure 6. example 2 of a daisy-chain data sequence w/wd0 = 32-bit word with a write command; wd0 writes data for device 0. the 0 refers to the position in the daisy chain (0 is c losest to the bus master). devices 1 and 2 are devices further down the chain. r/rd2 = 32-bit word with a read command; rd2 reads data from device 2. x = don? care (for x in the data or command position).
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface ______________________________________________________________________________________ 23 read-data format the max5732?ax5735 support daisy-chain connec- tions of multiple devices. the default (power-up) config- uration for the max5732?ax5735 assumes that the device may be part of a daisy chain of devices. dout follows din after 32 clock cycles. for a read command, dout provides read data (instead of the data value shifted in) in the next cycle following a cs rising edge. figures 5 and 6 show examples of daisy-chain data sequences. shutdown mode the max5732?ax5735 feature a software-controlled low-power shutdown mode. when bit 11 of the configu- ration register is a logic high, the analog section of the device is disabled, and the outputs go high impedance. in shutdown, supply current is reduced to 50?. data stored in the dac and input registers is retained, and the device outputs return to their previous values when the device is brought out of shutdown. the serial inter- face remains active while the device is in shutdown. power-up state the max5732?ax5735 monitor the four power supplies and maintain the output buffers in a known state until suffi- cient voltage is available to ensure that no output glitches occur. once the minimum voltage threshold has been passed, the device outputs come up in the clear state (all outputs = 0). for proper power sequencing, v ss must be applied first. power sequencing is not necessary if v ss is connected to agnd. controller device din dout 1 or 0 sclk cs max573_ dsp figure 7. stand-alone configuration controller device din dout 1 or 0 1 or 0 1 or 0 sclk cs max573_ din dout sclk cs max573_ din dout sclk cs max573_ dsp dsp dsp figure 8. example of a parallel configuration with read-back c1 c2 c0 a5 a4 a3 a2 a1 a0 sp sp sp sp sp sp sp d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 din(0) sclk cs ( c) cs (dsp) dout(0) or figure 9. read data timing when not daisy chained
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface 24 ______________________________________________________________________________________ applications information mems micromirror control the max5732/MAX5733 are the highest resolution 32- channel dacs available in the smallest footprint, mak- ing the devices ideal for optical mems mirror control (figure 10). a high-resolution dac forms the core ana- log block for controlling the x and y position of the mir- ror. as the density of the optical cross-connects increases, the number of dac channels also increases. by offering the highest resolution and the greatest den- sity, the max5732/MAX5733 improve performance and reduce the board footprint. automatic test equipment (ate) applications the max5734 includes many features suited for ate applications. the device is the most compact level-set- ting solution available for high-density pin electronics boards. the max5734 provides a -2.5v to +7.5v output voltage range (required by most ate applications). the offset dac simultaneously adjusts the voltage range of all 32 dacs, allowing optimization to the appli- cation. the remote-sense feature allows the pin elec- tronic voltages to be referenced to the ground potential at the dut site. the b grade linearity error of ?.44mv (max) is more than sufficient for most ate applications. the a grade device cuts this error to ?.22mv (max) for higher accuracy. the pipelined register architecture allows all 32 dacs to be updated simultaneously. this is valuable during test setups, as all values in the tester can be set and then updated in unison with a single command. this feature can be accessed through the serial port or the ldac input. the low output noise of the max5734 allows direct con- nection to the pin electronics, eliminating the cost and pc board area of external filtering. modern pin electronics integrated circuits (peics) are typically fabricated on high-speed processes with low adc max5732 MAX5733 dac0 hvdrv0 hvdrv31 dac31 14 to 16 bits voltage reference voltage reference dsp control algorithm position or optical feedback pga or fixed gain amps mems mirrors with x and y control thin-film filter or planar light wave separators with optical lenses mems mirrors with x and y control dwdm pipe optical lenses and collimators 14 to 16 bits dwdm pipe figure 10. mems mirror control
max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface ______________________________________________________________________________________ 25 selector guide part inl (max lsb) output voltage range (v) max5732actn ? 0 to +5 max5732bctn ?6 0 to +5 max5732cctn ?4 0 to +5 max5732aetn ? 0 to +5 max5732betn ?6 0 to +5 max5732cetn ?4 0 to +5 MAX5733actn ? 0 to +10 MAX5733bctn ?6 0 to +10 MAX5733cctn ?4 0 to +10 MAX5733aetn ? 0 to +10 MAX5733betn ?6 0 to +10 MAX5733cetn ?4 0 to +10 max5734actn ? -2.5 to +7.5 max5734bctn ?6 -2.5 to +7.5 max5734cctn ?4 -2.5 to +7.5 max5734aetn ? -2.5 to +7.5 max5734betn ?6 -2.5 to +7.5 max5734cetn ?4 -2.5 to +7.5 max5735actn ? -5 to +5 max5735bctn ?6 -5 to +5 max5735cctn ?4 -5 to +5 max5735aetn ? -5 to +5 max5735betn ?6 -5 to +5 max5735cetn ?4 -5 to +5 pin configuration top view max5732 MAX5733 max5734 max5735 v ss out3 agnd out4 out5 out6 out0 out1 out2 n.c. out7 out8 out9 av cc 11 10 9 8 7 6 5 4 3 2 14 13 12 1 exposed paddle cs 8mm x 8mm thin qfn-ep dsp sclk dout dv dd din ldac dgnd gs clr ref refgnd v ss av dd 20 19 18 17 16 24 23 22 21 15 26 25 28 27 29 30 31 32 33 34 35 36 37 38 agnd out23 out24 out25 out26 out27 out28 out29 out30 out31 39 v ss 40 41 out21 out22 42 av cc 46 47 48 49 50 43 44 45 51 out15 av dd refgnd av cc out16 out17 out18 out19 out20 52 out14 53 54 55 out11 out12 out13 56 out10 chip information transistor count: 152,000 process: bicmos breakdown voltages. some devices require external protection on their reference inputs to satisfy absolute maximum ratings. the max5734 features outputs that are almost rail-to-rail. this allows the av cc and v ss supplies to be set to voltages within the absolute maxi- mum ratings of the peic. this guarantees that the peic is protected in all situations. additional protection is provided by the max5734 glitch-free power-up into the clear state with all dac outputs set to approximately 0v. either the serial port or the clr input can assert the clear function. power supplies, bypassing, decoupling, and layout grounding and power-supply decoupling strongly influ- ence device performance. digital signals can couple through the reference input, power supplies, and ground connection. proper grounding and layout can reduce digital feedthrough and crosstalk. bypass all power sup- plies with an additional 0.1? and 1? on each pin, as close to the device as possible. refer to the max5732 max5735 evaluation kit for a suggested layout. the max5732?ax5735 have four separate power supplies. av dd powers the internal analog circuitry (except for the output buffers) and dv dd powers the digital section of the device. av cc and v ss power the output buffers. the max5732?ax5735 feature an exposed paddle on the backside of the package for improved power dissi- pation. the exposed paddle is electrically connected to v ss , and should be soldered to a large copper plane that shares the same potential. for more information on the exposed paddle qfn package, refer to the following website: http://pdfserv.maxim-ic.com/arpdf/appnotes/ 4hfan081.pdf
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. max5732?ax5735 32-channel, 16-bit, voltage-output dacs with serial interface package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 56l thin qfn.eps

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